Home
Author Info
Program |
16th International Workshop on
Worst-Case Execution Time Analysis
WCET
2016
Toulouse,
France, 5th July 2016
in
conjunction with the Euromicro
Conference on Real-Time Systems (ECRTS)
WCET 2016 is kindly supported by TACLe (www.tacle.eu), an
European
COST-Action on Timing Analysis on Code-Level.
Call for paper in plain text.
GOALS
AND TOPICS
A large
class of embedded systems is distinguished from general-purpose
computing systems by the need to satisfy strict requirements on
timing, often
under constraints on available resources. Predictable system
design is concerned
with the challenge of building systems for which timing
requirements can be
guaranteed a priori. Perhaps paradoxically, this problem has
become more
difficult by the introduction of performance-enhancing
architectural elements,
such as caches, pipelines, and multi-threading, which introduce
a large degree
of uncertainty and make timing guarantees harder to provide.
The WCET workshop focuses on the analysis and design of
timing-predictable
systems, with a strong emphasis on worst-case execution time
(WCET) analysis.
Topics of interest include all aspects of timing analysis and
timing-predictability. This includes (but is not limited to):
- WCET analysis for multi-threaded and multi-core systems
- Low-level timing analysis, modeling and analysis of processor
features
- Flow analysis for WCET, loop bounds, infeasible paths
- Measurement-based WCET analysis
- Different approaches to WCET computation
- Probabilistic timing analysis
- Tools for WCET analysis
- Integration of WCET and schedulability analysis
- Integration of WCET analysis in development processes
- Strategies to reduce the complexity of WCET analysis
- Processor and hardware design for timing predictability
- Program design for timing predictability
- Compiler-based optimization of worst-case timing
- Timing-predictable, resource-aware operating systems
- Experimental analysis of the timing behavior of processors
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
Statements which are innovative, controversial, or that present
new approaches
are specially sought.
FOCUS
OF THE 2016 EDITION
This year
we feature papers that provide tools in open source and provide
instructions how the evaluation results can be reproduced. The
PC will
explore those open source tools as part of the paper review
process.
WORKSHOP
STRUCTURE
The goal of
the workshop is to bring together people from academia, tool
vendors
and users in industry who are interested in all aspects of
timing predictability
of real-time systems. The workshop fosters a highly interactive
format with
ample time for in-depth discussions. It provides a relaxed forum
to present and
discuss new ideas, new research directions, and to review
current trends in this
area. The presentations will be kept short to leave plenty of
time for
interaction of attendees.
SUBMISSION
INSTRUCTIONS
Research
papers should present original research results not published or
submitted for publication in other forums. Accepted papers will
be published
via Schloss Dagstuhl's OASIcs online proceedings series,
indexed, with ISBN.
Authors of accepted papers agree to attend the workshop and to
present their
work during the workshop.
Papers submitted for the WCET workshop must be written in
English, must not
exceed 10 pages, should conform to the typesetting requirements
specified on the
workshop's website (http://wcet2016.compute.dtu.dk), and must be
submitted in
PDF format using the WCET workshop paper submission website.
Author names,
affiliations and self-references should not be anonymized.
Paper submission is via EasyChair at: https://easychair.org/conferences/?conf=wcet2016
IMPORTANT
DATES
Paper
Submission deadline: 26th May 2016 (23:59 GMT-12) (extended)
Notification of acceptance: 7th June 2016
Final paper submission: 17th June 2016
WCET Workshop: 5th July 2016
ECRTS Conference: 6-8th July 2016
PROGRAM
CHAIR
Martin
Schoeberl, Technical University of Denmark
PROGRAM
COMMITTEE
- Sebastian Altmeyer, University of
Luxembourg, Luxembourg
- Guillem Bernat, Rapita Systems, UK
- Hugues Casse, IRIT - Universite de
Toulouse, France
- Francisco J. Cazorla, Barcelona
Supercomputing Center, Spain
- Heiko Falk, TU Hamburg-Harburg, Germany
- Damien Hardy, IRISA, France
- Raimund Kirner, University of
Hertfordshire, UK
- Jens Knoop, Vienna University of
Technology, Austria
- Bjorn Lisper, Univ. College of Malardalen,
Sweden
- Claire Maiza, Grenoble INP/Verimag, France
- Enrico Mezzetti, Univ. of Padua, Italy
- Wolfgang Puffitsch, Technical University of
Denmark, Denmark
- Isabelle Puaut, IRISA, France
- Peter Puschner, TU Wien, Austria
- Harini Ramaprasad, University of North
Carolina at Charlotte, USA
- Christine Rochange, IRIT, France
- Martin Schoeberl, Technical University of
Denmark, Denmark
- Tullio Vardanega, Univ. of Padua, Italy
STEERING
COMMITTEE
- Guillem Bernat, Rapita Systems Ltd., UK
- Bjorn Lisper, Univ. College of Malardalen
- Isabelle Puaut, IRISA
- Peter Puschner, TU Wien
|